1 data sheet acquired from harris semiconductor schs207 features ? onboard oscillator ? common reset ? negative edge clocking ? typical f max = 50mhz at v cc = 5v, c l = 15pf, t a = 25 o c ? fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads ? wide operating temperature range . . . -55 o c to 125 o c ? balanced propagation delay and transition times ? signi?cant power reduction compared to lsttl logic ics ? hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v ? hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 m a at v ol , v oh pinout cd74hc4060, cd74hct4060 (pdip, soic) top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 q12 q13 q14 q6 q5 q7 gnd q4 v cc q8 q9 mr f i f o f o q10 february 1998 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1998 file number 1654.1 cd74hc4060, cd74hct4060 high speed cmos logic 14-stage binary counter with oscillator [ /title (cd74 hc406 0, cd74 hct40 60) / sub- j ect (high speed cmos
2 description the harris cd74hc4060 and cd74hct4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. the oscillator con?guration allows design of either rc or crystal oscillator circuits. a master reset input is provided which resets the counter to the all-0s state and disables the oscillator. a high level on the mr line accomplishes the reset function. all counter stages are master-slave ?ip-?ops. the state of the counter is advanced one step in binary order on the negative transition of f i (and f o). all inputs and outputs are buffered. schmitt trigger action on the input-pulse-line permits unlimited rise and fall times. in order to achieve a symmetrical waveform in the oscillator section the hct4060 input pulse switch points are the same as in the hc4060; only the mr input in the hct4060 has ttl switching levels. functional diagram ordering information part number temp. range ( o c) package pkg. no. cd74hc4060e -55 to 125 16 ld pdip e16.3 cd74hct4060e -55 to 125 16 ld pdip e16.3 cd74HC4060M -55 to 125 16 ld soic m16.15 cd74hct4060m -55 to 125 16 ld soic m16.15 notes: 1. when ordering, use the entire part number. add the suf?x 96 to obtain the variant in the tape and reel. 2. wafer and die for this part number is available which meets all electrical specifications. please contact your local sales office or harris customer service for ordering information. f i q4 q5 q6 q7 q9 q12 q14 f o f o mr q13 q10 q8 14-stage ripple counter and oscillator gnd = 8 v cc = 16 7 5 4 6 13 1 3 2 15 14 12 11 9 10 cd74hc4060, cd74hct4060
3 figure 1. logic block diagram truth table ? i mr output state - l no change l advance to next state x h all outputs are low ? 1q1 ff1 ? 1 q1 r ? 4q4 ff4 ? 4 q4 r ? 14 q14 ff14 ? 14 q14 r ? 5 q13 ff5 - ff13 ? 5 q13 r 723 5, 4, 6, 14, 13, 15, 1 q5 - q10, q12 mr 12 11 10 9 q14 q13 q4 ? o ? o ? 1 cd74hc4060, cd74hct4060
4 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc drain current, per output, i o for -0.5v < v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 3) q ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 3. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o cto125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage q outputs cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage q outputs ttl loads - - --- - - - - v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage q outputs cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage q outputs ttl loads - - --- - - - - v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v high-level output voltage f o output (pin 10) cmos loads v oh v cc or gnd -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v cd74hc4060, cd74hct4060
5 high-level output voltage f o output (pin 10) ttl loads note 6 v oh v cc or gnd -2.6 4.5 3.98 - - 3.84 - 3.7 - v -3.3 6 5.48 - - 5.34 - 5.2 - v low-level output voltage f o output (pin 10) cmos loads v ol v cc or gnd 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low-level output voltage f o output (pin 10) ttl loads v ol v cc or gnd 2.6 4.5 - - 0.26 - 0.33 - 0.4 v 3.3 6 - - 0.26 - 0.33 - 0.4 v high-level output voltage f o output (pin 9) ttl loads v oh v il or v ih -3.2 4.5 3.98 - - 3.84 - 3.7 - v -4.2 6 5.48 - - 5.34 - 5.2 - v low-level output voltage f o output (pin 9) ttl loads v ol v il or v ih -2.6 4.5 - - 0.26 - 0.33 - 0.4 v -3.3 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 m a quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 m a hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage q outputs cmos loads v oh v ih or v il note 5 -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage q outputs ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage q outputs cmos loads v ol v ih or v il note 5 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage q outputs ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v high-level output voltage f o output (pin 10) cmos loads v oh v cc or gnd -0.02 4.5 4.4 - - 4.4 - 4.4 - v high-level output voltage f o output (pin 10) ttl loads note 6 v oh v cc or gnd -2.6 4.5 3.98 - - 3.84 - 3.7 - v low-level output voltage f o output (pin 10) cmos loads v ol v cc or gnd 0.02 4.5 - - 0.1 - 0.1 - 0.1 v dc electrical speci?cations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o cto125 o c units v i (v) i o (ma) min typ max min max min max cd74hc4060, cd74hct4060
6 low-level output voltage f o output (pin 10) ttl loads v ol v cc or gnd 2.6 4.5 - - 0.26 - 0.33 - 0.4 v high-level output voltage f o output (pin 9) ttl loads v oh v il or v ih -3.2 4.5 3.98 - - 3.84 - 3.7 - v low-level output voltage f o output (pin 9) ttl loads v ol v ih or v il note 5 3.2 4.5 - 0.26 - 0.33 - 0.4 v input leakage current i i any voltage between v cc and gnd 0 5.5 - 0.1 - 1- 1 m a quiescent device current i cc v cc or gnd 0 5.5 - - 8 - 80 - 160 m a additional quiescent device current per input pin: 1 unit load d i cc (note 4) v cc -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 m a notes: 4. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. 5. for pin 11 v ih = 3.15v, v il = 0.9v. 6. limits not valid when pin 12 (instead of pin 11) is used as control input. dc electrical speci?cations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o cto125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads mr 0.35 note: unit load is d i cc limit speci?ed in dc electrical speci?ca- tions table, e.g. 360 m a max at 25 o c. prerequisite for switching speci?cations parameter symbol v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min typ max min typ max hc types maximum input pulse frequency t max 2 6 - - 5 - - 4 - - mhz 4.5 30 - - 25 - - 20 - - mhz 6 35 - - 29 - - 23 - - mhz input pulse width t w 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 614- -17- -20- -ns reset removal time t rem 2 100 - - 125 - - 150 - - ns 4.5 20 - - 25 - - 30 - - ns 617- -21- -26- -ns cd74hc4060, cd74hct4060
7 reset pulse width t w 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 614- -17- -20- -ns hct types maximum input, pulse frequency t max 4.5 30 - - 25 - - 20 - - mhz input pulse width t w 4.5 16 - - 20 - - 24 - - ns reset removal time t rem 4.5 26 - - 33 - - 39 - - ns reset pulse width t w 4.5 25 - - 31 - - 38 - - ns prerequisite for switching speci?cations (continued) parameter symbol v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min typ max min typ max switching speci?cations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay t plh , t phl c l = 50pf 2 - - 300 - 375 - 450 ns f i to q4 4.5 - - 60 - 75 - 90 ns c l = 15pf 5 - 25 - - - - - ns c l = 50pf 6 - - 51 - 64 - 78 ns q n to q n+1 t plh , t phl c l = 50pf 2 - - 80 - 100 - 120 ns 4.5 - - 16 - 20 - 24 ns c l = 15pf 5 - 6 - - - - - ns c l = 50pf 6 - - 14 - 17 - 20 ns mr to q n t phl c l = 50pf 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns c l = 15pf 5 - 14 - - - - - ns c l = 50pf 6 - - 30 - 37 - 45 ns output transition time t thl , t tlh c l = 50pf 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns input capacitance c i (tbd) propagation dissipation capacitance c pd - - -40- - - - - pf hct types propagation delay t plh , t phl c l = 50pf 2 - - - - - - - -ns f i to q4 4.5 - - 66 - 83 - 100 ns c l = 15pf 5 - 25 - - - - - -ns c l = 50pf 6 - - - - - - - -ns cd74hc4060, cd74hct4060
8 q n to q n+1 t plh , t phl c l = 50pf 2 - - - - - - - ns 4.5 - - 16 - 20 - 24 ns c l = 15pf 5 - 6 - - - - - ns c l = 50pf 6 - - - - - - - ns mr to q n t phl c l = 50pf 2 - - - - - - - ns 4.5 - - 44 - 55 - 66 ns c l = 15pf 5 - 17 - - - - - ns c l = 50pf 6 - - - - - - - ns output transition time t thl , t tlh c l = 50pf 2 - - - - - - - ns 4.5 - - 15 - 19 - 22 ns 6------ -ns input capacitance c i (tbd) propagation dissipation capacitance c pd - - -40- - - - - pf notes: 7. c pd is used to determine the dynamic power consumption, per package. 8. p d = c pd v cc 2 f i ? (c l v cc 2 f i /m) where m = 2 1 , 2 2 , 2 3 , ...2 14 , f i = input frequency, c l = output load capacitance. switching speci?cations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max typical limit values for r x and c x parameter test conditions voltage typical maximum limits r x minimum c x > 1000pf 2 1k w c x > 10pf 4.5 c x > 10pf 6 r x maximum c x > 10pf 2 20m w c x > 10pf 4.5 c x > 10pf 6 c x minimum r x > 10k w 2 10pf r x > 10k w 4.5 r x > 10k w 6 r x = 1k w 2 1000pf r x = 1k w 4.5 10pf r x = 1k w 6 10pf maximum astable oscillator frequency c x = 1000pf, r x = 1k w 2 0.5mhz (note 9) c x = 100pf, r x = 1k w 4.5 3mhz (note 9) c x = 100pf, r x = 1k w 6 3mhz (note 9) note: 9. at very high frequencies f = 1/2.2 r x c x no longer gives an yaccurate approximation. note: osc frequency ? 1/2.2 r x c x for 1m w > r x > 1k w , c x > 10pf, f < 1mhz figure 2. frequency of on-board oscillator as a function of c x and r x 10 2 10 1 10 -1 10 -2 10 -3 10 -4 10 -5 10 -1 10 0 10 10 2 10 3 10 4 10 5 10 6 oscillator frequency (hz) c x ( m f) t a = 25 o c r x = 1k w 10k w 100k w 1m w 10m w cd74hc4060, cd74hct4060
9 typical performance curves note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 3. hc clock pulse rise and fall times and pulse width note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 4. hct clock pulse rise and fall times and pulse width figure 5. hc and hct transition times and propaga- tion delay times, combination logic figure 6. hct transition times and propagation delay times, combination logic clock 90% 50% 10% gnd v cc t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = fc l i clock 2.7v 1.3v 0.3v gnd 3v t r c l = 6ns t f c l = 6ns 1.3v 1.3v t wl t wh 0.3v t wl + t wh = fc l i t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90%
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